Rdma based real-time video client playback architecture

ABSTRACT

A client playback architecture for a media content distribution system is provided. In the preferred embodiment, the client playback architecture is a Remote Direct Memory Access (RDMA) based architecture. The RDMA based architecture enables the client playback device to obtain media content from a central server in real-time or in substantially real-time as the media content is needed for playback at the client playback device. More specifically, the playback device includes RDMA enabled playback circuitry operating to perform RDMA transfers for select media content, buffer the media content received as a result of the RDMA transfers, and provide the media content for presentation to one or more associated viewers via one or more audio/video interfaces.

RELATED APPLICATIONS

This patent application claims priority to and is a continuation ofco-pending U.S. patent application Ser. No. 14/043,587, entitled “RDMABASED REAL-TIME VIDEO CLIENT PLAYBACK ARCHITECTURE,” filed on Oct. 1,2013, now U.S. Pat. No. 9,032,641 which claims priority to and is acontinuation of U.S. patent Ser. No. 13/178,954 entitled “RDMA BASEDREAL-TIME VIDEO CLIENT PLAYBACK ARCHITECTURE,” filed on Jul. 8, 2011,now U.S. Pat. No. 8,549,091 which claims priority to and is acontinuation of U.S. patent application Ser. No. 11/831,228, entitled“RDMA BASED REAL-TIME VIDEO CLIENT PLAYBACK ARCHITECTURE,” filed on Jul.31, 2007, now U.S. Pat. No. 7,996,482, the disclosures of each of whichare hereby incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present invention relates to a media content distribution system andmore particularly relates to an architecture for a client playbackdevice in a media content distribution system.

BACKGROUND

Many new and novel systems are emerging for narrowcasting ofadvertisements in media distribution systems such as, for example,digital television distribution systems. As a result of narrowcastingadvertisements, higher levels of advertisement-based revenue can beobtained. However as narrowcast becomes more targeted and the number ofusers in the system grows, current centralized media contentdistribution systems do not efficiently scale for cost, size, and power.Thus, new architectures are needed to allow real-time late-binding ofadvertisements while minimizing loading on these centralized mediacontent distribution systems.

SUMMARY

The present invention provides a client playback architecture for amedia content distribution system. In the preferred embodiment, theclient architecture is a Remote Direct Memory Access (RDMA) basedarchitecture. The RDMA based architecture enables the client playbackdevice to obtain media content from a central server in real-time or insubstantially real-time as the media content is needed for playback atthe client playback device. More specifically, the playback deviceincludes RDMA enabled playback circuitry operating to perform RDMAtransfers for select media content, buffer the media content received asa result of the RDMA transfers, and provide the media content forpresentation to one or more associated viewers via one or moreaudio/video interfaces.

In one embodiment, the RDMA playback circuitry includes an array of RDMAenabled buffers, an array of playback buffers, and switching circuitryinterconnecting the array of RDMA enabled buffers to the array ofplayback buffers. In operation, when playback of select media content isdesired, RDMA is utilized to transfer the select media content to acorresponding RDMA enabled buffer. As the select media content is beingtransferred to the RDMA enabled buffer, the media content is transferredto a desired playback buffer via the switching circuitry according to aplayback clock. The playback buffer stores and optionally processes themedia content for presentation to one or more associated viewers via anassociated interface.

Those skilled in the art will appreciate the scope of the presentinvention and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the invention, andtogether with the description serve to explain the principles of theinvention.

FIG. 1 illustrates a media content delivery system 10 incorporating aRemote Direct Memory Access (RDMA) enabled client architecture accordingto one embodiment of the present invention;

FIG. 2 illustrates an exemplary RDMA client architecture according toone embodiment of the present invention;

FIG. 3 is a block diagram of the RDMA enabled playback circuitry of FIG.2 according to one embodiment of the present invention;

FIG. 4 is a block diagram of one of the RDMA enabled First-In-First-Out(FIFO) buffer circuits of FIG. 3 according to one embodiment of thepresent invention;

FIG. 5 is a flow chart illustrating the operation of the RDMA enabledFIFO buffer circuit of FIG. 4 according to one embodiment of the presentinvention;

FIG. 6 is a more detailed illustration of one step of the processillustrated in FIG. 5 according to one embodiment of the presentinvention;

FIG. 7 is a more detailed illustration of another step of the processillustrated in FIG. 5 according to one embodiment of the presentinvention;

FIG. 8 is a block diagram of one of the playback buffer circuits of FIG.3 according to one embodiment of the present invention; and

FIG. 9 is a flow chart illustrating the operation of the playback buffercircuit of FIG. 8 according to one embodiment of the present invention.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the invention and illustratethe best mode of practicing the invention. Upon reading the followingdescription in light of the accompanying drawing figures, those skilledin the art will understand the concepts of the invention and willrecognize applications of these concepts not particularly addressedherein. It should be understood that these concepts and applicationsfall within the scope of the disclosure and the accompanying claims.

FIG. 1 illustrates a media content delivery system 10 incorporating aRemote Direct Memory Access (RDMA) enabled client architecture accordingto one embodiment of the present invention. Note that while RDMA isdiscussed herein as the preferred embodiment, the present invention isnot limited thereto. Further, as used herein, “RDMA” is not necessarilyany particular RDMA protocol but is rather any digital content transferscheme enabling transfer of digital content from the memory or otherdigital storage unit of one device to the memory or other digitalstorage unit of another device via a network with minimal or no CentralProcessing Unit (CPU) and/or operating system utilization.

In general, the system 10 includes a centralized media content server 12interconnected to a number of set-top box (STB) functions 14-1 through14-N₁ via a network 16, which in this example is a Local Area Network(LAN) 16. The LAN 16 may be any type of wired and/or wireless LAN. Inone embodiment, the LAN 16 provides a 10 Gigabits per second (Gbps) orhigher transfer rate using InfiniBand (IB) or some other RDMA enabledprotocol. The centralized media content server 12 may additionally oralternatively be interconnected to a number of STB functions 18-1through 18-N₂ via a network 20, which in this example is a Wide AreaNetwork (WAN) 20. The WAN 20 may be wired, wireless, or a combinationthereof. In one embodiment, the WAN 20 is an optical network providing a10 Gbps or higher transfer rate. RDMA over Transfer ControlProtocol/Internet Protocol (TCP/IP), or iWARP, may be used in theprotocol stack to provide reliable transport of RDMA traffic over theWAN 20. Note that, preferably, the centralized media content server 12serves only the STB functions 14-1 through 14-N₁ via the LAN 16 or theSTB functions 18-1 through 18-N₂ via the WAN 20. In the case of the STBfunctions 14-1 through 14-N₁, the centralized media content server 12 ispreferably a server located on the same premises as the STB functions14-1 through 14-N₁. For example, the centralized media content server 12and the STB functions 14-1 through 14-N₁ may be located in a particularuser's home. In the case of the STB functions 18-1 through 18-N₂, thecentralized media content server 12 may be located at, for example, aheadend of a video distribution network.

The STB functions 14-1 through 14-N₁ and 18-1 through 18-N₂ mayalternatively be referred to herein as client devices. Each of the STBfunctions 14-1 through 14-N₁ and 18-1 through 18-N₂ may be, for example,a set-top box similar to those used in traditional digital televisiondelivery systems, a component of a set-top box, a personal computer, acomponent of a personal computer, a portable media player similar to aniPod®, a mobile telephone, a Personal Digital Assistant (PDA), or thelike. As discussed below, the STB functions 14-1 through 14-N₁ and 18-1through 18-N₂ incorporate RDMA enabled playback functions which enablethe STB functions 14-1 through 14-N₁ and 18-1 through 18-N₂ to utilizeRDMA to obtain desired media content from the centralized media contentserver 12.

The centralized media content server 12 hosts media content 22. Themedia content may include, for example, video content such as movies,television programs, or video clips; audio content such as songs orradio programs; streaming video content such as broadcast televisionchannels or IPTV channels; streaming audio content such as broadcastradio stations; advertisement content; or the like, or any combinationthereof. The centralized media content server 12 also includes an RDMAenabled network interface 24. In the illustrated embodiment, the RDMAenabled network interface 24 includes a LAN optimized protocol stack 26and/or a WAN optimized protocol stack 28. The LAN optimized protocolstack 26 may use the IB protocol or similar RDMA enabled protocol tocarry RDMA traffic over the LAN 16. The WAN optimized protocol stack 28may use RDMA over TCP/IP or similar RDMA enabled protocol to carry RDMAtraffic over the WAN 20.

FIG. 2 is a functional block diagram of the STB function 14-1 of FIG. 1.This discussion is equally applicable to the other STB functions 14-2through 14-N₁ and 18-1 through 18-N₂. The STB function 14-1 includesRDMA enabled playback circuitry 30 and a driver function 32 forcontrolling the RDMA enabled playback circuitry 30. The RDMA enabledplayback circuitry 30 is preferably implemented in hardware. Forexample, the RDMA enabled playback circuitry 30 may be implemented inone or more Field Programmable Gate Arrays (FPGAs), one or moreApplication Specific Integrated Circuits (ASICs), or the like. Thedriver 32 may be implemented in hardware, software, or a combinationthereof.

As discussed below in detail, under the control of the driver 32, theRDMA enabled playback circuitry 30 operates to effect RDMA transfers ofselect media content from the centralized media content server 12(FIG. 1) to the STB function 14-1 via an RDMA enabled network interface34. The RDMA enabled network interface 34 includes a physical layer 36,a link layer 38, a routing layer 40, a transport layer 42, and an RDMAlayer 44. The physical layer 36, the link layer 38, the routing layer40, and the transport layer 42 are similar to those in traditionalnetwork interfaces. For example, the layers 36-42 may be the same asthose in any industry complaint LAN based network interface card (NIC).Note that if the LAN 16 or WAN 20 is a Cable Television (CATV) network,the layers 36-42 may be a Data Over Cable Services InterfaceSpecifications (DOCSIS) based protocol stack or a LAN/WAN protocol stacklocated inside a DOCSIS based modem or firewall.

The RDMA enabled playback circuitry 30 also operates to output thereceived video content using one or more audio/video (A/V) interfaces 46for presentation to one or more associated users via a viewer interface48. The A/V interfaces 46 may include, for example, a High DefinitionMultimedia Interface (HDMI) with or without High-bandwidth DigitalContent Protection (HDCP) or similar Digital Rights Management (DRM)technology, a Digital Video Interface (DVI), a component videointerface, an S-Video interface, a component A/V interface, or the like,or any combination thereof. The viewer interface 48 may be, for example,a television or other display, a sound system, or the like, or acombination thereof. While the viewer interface 48 is illustrated aspart of the STB function 14-1, the present invention is not limitedthereto. The viewer interface 48 may alternatively be a separate device.

In this example, the viewer interface 48 also includes one or more userinput components such as, for example, input buttons or dials, a keypad,a wireless remote control, or the like. As such, the STB function 14-1may also include a client control function 50 operating to receiveinputs from the one or more associated users and to either: (1) pass theuser inputs to the RDMA enabled playback circuitry 30, the driver 32,the A/V interface 46, a controller 52 of the STB function 14-1, or anycombination thereof or (2) process the user inputs and control one ormore of the RDMA enabled playback circuitry 30, the driver 32, the A/Vinterface 46, and the controller 52 based on the user inputs. Forexample, the client control function 50 may receive user inputs such ascontent selection inputs and playback control inputs such as pause,fast-forward, rewind, or the like. Upon receiving a content selectioninput, the client control function 50 may either provide the contentselection input to the driver 32 or control the driver 32 to initiateplayback of the selected media content. Similarly, upon receiving aplayback control input, the client control function 50 may eitherprovide the playback control input to the driver 32 and/or the RDMAenabled playback circuitry 30 or control the driver 32 and/or the RDMAenabled playback circuitry 30 according to the playback control input.

The controller 52 may be used to perform various functions. For example,in one embodiment, the centralized media content server 12 (FIG. 1)publishes a mapping providing RDMA address ranges for all or at least aportion of the media content items hosted by the centralized mediacontent server 12. The mapping may also include metadata describing themedia content items such as, for example, titles, content type, genre,and the like, or any combination thereof. The controller 52 may operateto receive or otherwise obtain the mapping from the centralized mediacontent server 12 via the RDMA enabled network interface 34. Note that,as illustrated, the controller 52 is connected to the LAN 16 via thelayers 36-42 of the RDMA enabled network interface 34 and, optionally,one or more session and/or Open Systems Interconnection (OSI) layers 54.The controller 52 may perform other functions such as, for example,effecting presentation of an Electronic Programming Guide (EPG), menus,or the like to the one or more associated users via the A/V interface 46to enable the one or more associated users to select media content forplayback.

FIG. 3 is a block diagram of the RDMA enabled playback circuitry 30 ofFIG. 2 according to one embodiment of the present invention. In thisembodiment, the RDMA enabled playback circuitry 30 includes an array ofRDMA enabled First-In-First-Out (FIFO) buffer circuits 56-1 through 56-Xand an array of playback buffer circuits 58-1 through 58-Yinterconnected by a bi-directional crossbar switch 60 to form atwo-stage buffering architecture. Both the array of RDMA enabled FIFObuffer circuits 56-1 through 56-X and the array of playback buffercircuits 58-1 through 58-Y are scalable, where the number of RDMAenabled FIFO buffer circuits 56-1 through 56-Y and the number ofplayback buffer circuits 58-1 through 58-Y depend on the particularimplementation.

As one example of the use of the array of RDMA enabled FIFO buffercircuits 56-1 through 56-X, the STB function 14-1 may performlate-binding of targeted advertisements to select video content. Morespecifically, upon receiving a content selection from the user, thedriver 32 may assign the RDMA enabled FIFO buffer 56-1 to obtain theselected video content and assign the RDMA enabled FIFO buffer 56-2 toobtain targeted advertisements to be inserted into the selected videocontent during playback. Assuming, for example, that the select videocontent is being presented to the viewer via the playback buffer circuit58-1, the driver 32 controls the crossbar switch 60 such that theplayback buffer circuit 58-1 is connected to the RDMA enabled FIFObuffer circuit 56-1 during playback of the select video content and isswitched to the RDMA enabled FIFO buffer circuit 56-2 to present thetargeted advertisements during advertisement (ad) slots. For moreinformation regarding an exemplary late-binding method for a central orremote headend of a video distribution system that may be used toperform late-binding in the STB function 14-1, the interested reader isdirected to U.S. patent application Ser. No. 11/685,479, entitledLATE-BINDING OF ADVERTISEMENTS USING RDMA CONNECTIVITY, filed on Mar.13, 2007 and U.S. patent application Ser. No. 11/760,013, entitledMULTI-CLIENT STREAMER WITH LATE BINDING OF AD CONTENT, filed on Jun. 8,2007, both of which are hereby incorporated herein by reference in theirentireties.

As another example of the use of the array of RDMA enabled FIFO buffercircuits 56-1 through 56-X, the STB function 14-1 may utilize multipleRDMA enabled FIFO buffer circuits 56-1, 56-X to provide aPicture-In-Picture (PIP) feature or to otherwise present multiple mediacontent items simultaneously.

FIG. 4 is a block diagram of the RDMA enabled FIFO buffer circuit 56-1according to one embodiment of the present invention. This discussion isequally applicable to the other RDMA enabled FIFO buffer circuits 56-2through 56-X. The RDMA enabled FIFO buffer circuit 56-1 includes a FIFObuffer 62, an RDMA data mover function 64, and an RDMA address comparefunction 66. The FIFO buffer 62 may be implemented in any type of memoryand, in this embodiment, has a number of programmable thresholdsettings. In this example, the FIFO buffer 62 has an “empty” thresholdsetting, an “almost empty” threshold setting, a “half full” thresholdsetting, a “half empty” threshold setting which typically corresponds tothe half full threshold setting, an “almost full” threshold setting, anda “full” threshold setting. The FIFO buffer 62 provides a FIFO statusoutput that is indicative of the status of the FIFO buffer 62. Morespecifically, the FIFO status output is in an “empty” state when theFIFO buffer 62 is empty, in an “almost empty” state when the amount ofdata stored in the FIFO buffer 62 is less than or equal to the almostempty threshold setting, in a “half empty” state when the amount of datastored in the FIFO buffer 62 is less than or equal to the half emptythreshold setting but greater than the almost empty threshold setting,in a “half full” state when the amount of data stored in the FIFO buffer62 is greater than the half full threshold setting but less than thealmost full threshold setting, in an “almost full” state when the amountof data stored in the FIFO buffer 62 is greater than the almost fullthreshold setting, and a “full” state when the FIFO buffer is full. Inthis example, the FIFO status is provided to the playback buffer circuit58-1, 58-Y to which the FIFO buffer 62 is connected via the crossbarswitch 60 as a FIFO output data ready signal.

In operation, when media content is selected for playback, the driver 32identifies an RDMA address range for the selected media content at thecentralized media content server 12 from, for example, the mappingpublished by the centralized media content server 12. The driver 32 thenprovides the RDMA address range to the RDMA data mover function 64 ofthe RDMA enabled FIFO buffer circuit 56-1, which has been allocated forthe selected media content by, for example, the controller 52. Uponreceiving the RDMA address range, the RDMA data mover function 64generally operates to determine the available space in the FIFO buffer62 and generates an RDMA transfer request for at least a segment of theRDMA address range based on the available space in the FIFO buffer 62.The RDMA data mover function 64 then provides the RDMA transfer requestto the RDMA layer 44 (FIG. 2) of the RDMA enabled network interface 34(FIG. 2).

Thereafter, as data is received from the RDMA layer 44, the RDMA addresscompare function 66 compares an address of the received data (“ReceivedRDMA address”) to a next anticipated RDMA address to determine whetherthe received data is data received in response to the RDMA transferrequest of the RDMA data mover function 64. This is important where morethan one of the RDMA enabled FIFO buffer circuits 56-1 through 56-X haveissued concurrent RDMA transfer requests. By comparing the RDMA addressof the received data to the next anticipated RDMA address for the issuedRDMA transfer request, the RDMA address compare function 66 ensures thatonly the requested data is clocked into the FIFO buffer 62. If the RDMAaddress of the received data is the next anticipated RDMA address, theRDMA address compare function 66 toggles a gated FIFO input clockprovided to the FIFO buffer 62 to clock the received data into the FIFObuffer 62. The data may be clocked in as a bit, byte, word, or otherformat appropriate to the RDMA enabled network interface 34 and the FIFObuffer 62. The RDMA data mover function 64 then increments the nextanticipated RDMA address, and the process continues until all of therequested data is stored in the FIFO buffer 62.

Note that, in an alternative embodiment, the data received from the RDMAlayer 44 is a block of data from a block of RDMA addresses. Thus,additional circuitry may be used within or around the RDMA addresscompare function 66 to correctly clock the data into the FIFO buffer 62.Also, additional circuitry may be used to increment the next anticipatedRDMA address value in response to receiving data for a block of RDMAaddresses rather than receiving data for each RDMA address separately.

Once all of the data for the RDMA transfer request has been received,the RDMA data mover function 64 monitors the FIFO buffer 62 to determinewhen at least a threshold amount of space is available before issuingthe next RDMA transfer request, if any, for the selected media content.The threshold amount may be, for example, when the status of the FIFObuffer 62 is equal to or less than almost full. If the threshold amountof space is available, the RDMA data mover function 64 generates an RDMAtransfer request for a next segment of the address range for theselected media content item. From this point, the process continuesuntil the data for the entire RDMA address range has been transferred tothe FIFO buffer 62. Once the transfer is complete, the RDMA data moverfunction 64 provides a “transfer complete” signal to the driver 32. Notethat the RDMA data mover function 64 may provide feedback to the driver32 if the transfer failed, if a FIFO overflow condition exists, or if aFIFO underflow condition exists. If the transfer fails or if playback ofthe selected media content is terminated, the driver 32 may instruct theRDMA data mover function 64 to clear the current transfer and clear theFIFO buffer 62.

While the data corresponding to the selected media content item is beingtransferred to the FIFO buffer 62, the data is also being clocked out ofthe FIFO buffer 62 by a FIFO output clock. As discussed below, the FIFOoutput clock is a streaming video playback clock provided by theplayback buffer circuit 58-1, 58-Y (FIG. 3) to which the RDMA enabledFIFO buffer circuit 56-1 is connected by the crossbar switch 60. In thisexample, assume that the RDMA enabled FIFO buffer circuit 56-1 isconnected to the playback buffer circuit 58-1. The streaming video clockof the playback buffer circuit 58-1 is controlled such that the data istransferred from the FIFO buffer 62 to the playback buffer circuit 58-1at a rate desired for playback. Thus, for example, if the viewer pausesplayback, the streaming video clock is controlled such that data is notclocked out of the FIFO buffer 62. However, as a result of the two-stagebuffer architecture of the RDMA enabled playback circuitry 30, datacontinues to be transferred to the FIFO buffer 62 regardless of thestate of the streaming video clock until the FIFO buffer 62 is full.

FIG. 5 is a flow chart illustrating the operation of the RDMA data moverfunction 64 according to one embodiment of the present invention. First,the RDMA data mover function 64 receives an RDMA starting address and anRDMA ending address from the driver 32 (step 100). The RDMA startingaddress and the RDMA ending address define the RDMA address range forselect video content hosted by the centralized media content server 12(FIG. 1). As discussed above, when the viewer requests select videocontent, the driver 32 identifies the RDMA address range for the selectvideo content using, for example, the mapping from the centralized mediacontent server 12. Upon receiving the RDMA starting and endingaddresses, the RDMA data mover function 64 determines whether the FIFObuffer 62 is full (step 102). In one embodiment, if the FIFO buffer 62is full, the RDMA data mover function 64 continues to monitor the statusof the FIFO buffer 62 until the FIFO is no longer full. In anotherembodiment, the RDMA data mover function 64 notifies the driver 32 thatthe FIFO buffer 62 is full and then waits for the driver 32 to reset, orclear, the FIFO buffer 62 (step 104).

If the FIFO buffer 62 is not full, or alternatively after the FIFObuffer 62 has been reset, the RDMA data mover function 64 sets astarting address for an RDMA transfer request to the RDMA startingaddress of the RDMA address range for the select video content (step106). The RDMA data mover function 64 then determines whether the FIFObuffer 62 is almost full (step 108). If the status of the FIFO buffer 62is almost full, the RDMA data mover function 64 waits until a sufficientamount of data has been clocked out of the FIFO buffer 62 to reduce thestatus of the FIFO buffer 62 below almost full. The RDMA data moverfunction 64 then calculates an ending address for the RDMA transferrequest based on an amount of space available in the FIFO buffer 62, asdiscussed below in detail (step 110). In the typical scenario, the FIFObuffer 62 is not large enough to store all of the select video content.As such, the RDMA data mover function 64 sets the ending address for theRDMA transfer request based on a determination of the amount of spaceavailable in the FIFO buffer 62 or, in other words, a determination ofthe largest data block size that can be guaranteed to fit into the FIFObuffer 62.

Once the starting address and ending address for the RDMA transferrequest are set, the RDMA data mover function 64 initiates and completesan RDMA transfer using the RDMA transfer request (step 112). Morespecifically, the RDMA data mover function 64 initiates the RDMAtransfer by providing the RDMA transfer request to the RDMA layer 44 ofthe RDMA enabled network interface 34 (FIG. 2). Thereafter, the RDMAdata mover function 64 completes the RDMA transfer by programming theRDMA address compare function 66 (FIG. 4) with the next anticipated RDMAaddress values such that the data received in response to the RDMAtransfer request is stored in the FIFO buffer 62.

Once the RDMA transfer is complete, the RDMA data mover function 64determines whether the ending address for the RDMA transfer request isequal to the RDMA ending address for the RDMA address range for theselect video content (step 114). If so, the RDMA data mover function 64notifies the driver 32 that the RDMA transfer is complete (step 116),and the process returns to step 100. If not, the RDMA data moverfunction 64 sets a starting address for a next RDMA transfer request tothe ending address of the RDMA transfer request plus one (step 118), andthe process returns to step 108. The process is repeated until thetransfer of the entire RDMA address range for the select video contentis complete or until the RDMA transfer is terminated as a result of, forexample, the viewer selecting new video content for playback.

FIG. 6 is a more detailed illustration of step 110 of FIG. 5 accordingto one embodiment of the present invention. In order to calculate theending address for the RDMA transfer request, the RDMA data moverfunction 64 first determines whether the status of the FIFO buffer 62 ishalf full (step 200). If so, the actual amount of data stored in theFIFO buffer 62 is in the range between the half full threshold settingand the almost full threshold setting of the FIFO buffer 62. As such,the RDMA data mover function 64 sets the range of the RDMA transferrequest, or size of the segment to be transferred by the RDMA transferrequest, equal to the full threshold setting of the FIFO buffer 62 minusthe almost full threshold setting of the FIFO buffer 62 (step 202). Theprocess proceeds to step 214. If the FIFO buffer 62 is not half full,the RDMA data mover 64 then determines whether the status of the FIFObuffer 62 is almost empty (step 204). If not, the amount of data storedin the FIFO buffer 62 is between the almost empty threshold setting andthe half full/empty threshold setting. As such, the RDMA data moverfunction 64 sets the range of the RDMA transfer request, or size of thesegment to be transferred by the RDMA transfer request, equal to thefull threshold setting of the FIFO buffer 62 minus the half empty/fullthreshold setting of the FIFO 6 buffer 2 (step 206). The process thenproceeds to step 214. If the FIFO buffer 62 is almost empty, the RDMAdata mover 64 then determines whether the status of the FIFO buffer 62is empty (step 208). If not, the amount of data stored in the FIFObuffer 62 is between the empty threshold setting and the almost emptythreshold setting. As such, the RDMA data mover function 64 sets therange of the RDMA transfer request, or size of the segment to betransferred by the RDMA transfer request, equal to the full thresholdsetting of the FIFO buffer 62 minus the almost empty threshold settingof the FIFO buffer 62 (step 210). The process then proceeds to step 214.If the FIFO buffer 62 is empty, the RDMA data mover function 64 sets therange of the RDMA transfer request, or size of the segment to betransferred by the RDMA transfer request, equal to the full thresholdsetting of the FIFO buffer 62 minus the empty threshold setting of theFIFO buffer 62, which is preferably the full size or substantially thefull size of the FIFO buffer 62 (step 212). The process then proceeds tostep 214.

At this point, the RDMA data mover function 64 sets the ending addressof the RDMA transfer request to a value equal to the starting address ofthe RDMA transfer request plus the range of the RDMA transfer requestdetermined in steps 200-212 (step 214). The RDMA data mover function 64then determines whether the ending address for the RDMA transfer requestis greater than the RDMA ending address for the RDMA address range forthe select video content (step 216). If not, the process proceeds tostep 112 of FIG. 5. If so, the RDMA data mover function 64 sets theending address of the RDMA transfer request to the RDMA ending addressfor the RDMA address range for the select video content (step 218), andthe process then proceeds to step 112 of FIG. 5.

FIG. 7 is a more detailed illustration of step 112 of FIG. 5 accordingto one embodiment of the present invention. In order to initiate andcomplete the RDMA transfer request, the RDMA data mover function 64first sends the RDMA transfer request to the RDMA layer 44 (FIG. 2) ofthe RDMA enabled network interface 34 (step 300). The RDMA data moverfunction 64 then sets the next anticipated RDMA address to the startingaddress of the RDMA transfer request (step 302). As discussed above, theRDMA address compare function 66 compares the next anticipated RDMAaddress to the RDMA address of data received from the RDMA layer 44.Since two or more of the RDMA enabled FIFO buffer circuits 56-1 through56-X may be concurrently requesting RDMA data, the RDMA address comparefunction 66 ensures that only data received in response to the RDMAtransfer request issued by the RDMA data mover function 64 is clockedinto the FIFO buffer 62.

The RDMA data mover function 64 then monitors the gated FIFO input clockoutput by the RDMA address compare function 66 to determine whether thegated FIFO input clock has toggled (step 304). Note that the gated FIFOinput clock is toggled by the RDMA address compare function 66 inresponse to receiving an RDMA address that is equal to the nextanticipated RDMA address for the transfer in order to clock thecorresponding data into the FIFO buffer 62. If the gated FIFO inputclock has not toggled, the RDMA data mover function 64 determineswhether a timeout period has expired for the RDMA transfer request (step306). If so, the RDMA data mover function 64 notifies the driver 32 thatthe RDMA transfer request has failed (step 308). If the timeout periodhas not expired, the process returns to step 304.

Once the gated FIFO input clock has toggled to clock the data for thenext anticipated RDMA address into the FIFO buffer 62, the RDMA datamover function 64 determines whether the next anticipated RDMA address,which is the RDMA address of the data just clocked into the FIFO buffer62, is equal to the ending address of the RDMA transfer request (step310). If so, the process proceeds to step 114 of FIG. 5. If not, theRDMA data mover function 64 increments the next anticipated RDMA addressto be received by one (step 312). At this point, the process returns tostep 304 and is repeated until the RDMA transfer is complete.

FIG. 8 is a block diagram of the playback buffer circuit 56-1 accordingto one embodiment of the present invention. This discussion is equallyapplicable to the other playback buffer circuits 56-2 through 56-Y. Inthis embodiment, the playback buffer circuit 56-1 includes a videoprocessing function 68 and an A/V playback buffer 70 controlled by aclient playback control function 72 and a video buffer monitoring andtransfer control function 74. The video processing function 68 isoptional and may be implemented in hardware, software, or a combinationthereof. In one embodiment, the video processing function 68 may performoperations such as decoding and decompressing the video content receivedfrom the RDMA enabled FIFO buffer circuit 56-1, 56-X to which it isconnected via the crossbar switch 60 such that the video content isready for presentation without additional delay. In addition oralternatively, if PIP or some similar feature is supported, the videoprocessing function 68 may receive data from two or more of the RDMAenabled FIFO buffer circuits 56-1 through 56-X and process the data toprovide the PIP or similar feature. The A/V playback buffer 70 is anytype of buffer suitable for storing the video content from the videoprocessing function for presentation to the one or more viewers via theA/V interface 46. Note that the A/V playback buffer 70 may include anycontrol circuits needed or desired to enable playback control featuressuch as rewinding, pausing, fast-forwarding, or the like.

The client playback control function 72 may be implemented in software,hardware, or a combination thereof. For example, the client playbackcontrol function 72 may be implemented as a software application storedby the controller 52 (FIG. 2). The video buffer monitoring and transfercontrol function 74 may be implemented in software, hardware, or acombination thereof. For example, if the STB function 14-1 is a set-topbox, the video buffer monitoring and transfer control function 74 may beimplemented as an Open Cable Application Platform (OCAP) application.

The video buffer monitoring and transfer control function 74 generallyoperates to manage a streaming video clock 76 based on the status of theA/V playback buffer 70 and/or requests from the client playback controlfunction 72. The streaming video clock 76 is provided to clock data outof the FIFO buffer 62 of the connected RDMA enabled FIFO buffer circuit56-1, 56-X to the video processing function 68 via the crossbar switch60 at a desired clock rate. The streaming video clock 76 may be enabledor disabled by the video buffer monitoring and transfer control function74. For example, the streaming video clock 76 may be disabled when auser input has been received from the viewer requesting that playback bepaused. More specifically, if the viewer sends a request to pauseplayback, the client playback control function 72 may relay the pauserequest to the video buffer monitoring and transfer control function 74.The video buffer monitoring and transfer control function 74 may thenmonitor the A/V playback buffer 70 to allow data to continue to betransferred to the A/V playback buffer 70 until, for example, the A/Vplayback buffer 70 is full. When the A/V playback buffer 70 is full, thevideo buffer monitoring and transfer control function 74 may disable thestreaming video clock 76 to suspend the transfer of data from the RDMAenabled FIFO buffer circuit 56-1, 56-X until the A/V playback buffer 70is no longer full as a result of, for example, the viewer resumingplayback. Alternatively, the video buffer monitoring and transfercontrol function 74 may disable the streaming video clock 76 as soon asthe pause request is received and subsequently re-enable the streamingvideo clock 76 when playback is resumed.

FIG. 9 illustrates the operation of the playback buffer circuit 58-1 ofFIG. 8 according to one embodiment of the present invention. First, theclient playback control function 72 initializes the video buffermonitoring and transfer control function 74 (step 400). The video buffermonitoring and transfer control function 74 then checks or otherwiseobtains the status of the A/V playback buffer 70 (step 402). Next, thevideo buffer monitoring and transfer control function 74 determineswhether the A/V playback buffer 70 needs more data and whether the dataready signal from the connected RDMA enabled FIFO buffer circuit 56-1,56-X is active (step 404). If the A/V playback buffer 70 needs more dataand the data ready signal is active, the video buffer monitoring andtransfer control function 74 determines whether the streaming videoclock 76 is enabled (step 406). If the streaming video clock is enabled,the process returns to step 402. If the streaming video clock 76 is notenabled, the video buffer monitoring and transfer control function 74enables the streaming video clock 76 (step 408). The process thenreturns to step 402.

Note that upon enabling the streaming video clock 76, data begins to beclocked from the FIFO buffer 62 of the RDMA enabled FIFO buffer circuit56-1, 56-X to which the playback buffer circuit 58-1 is connected viathe crossbar switch 60. The data may be clocked from the FIFO buffer 62as bits, bytes, words, or other appropriate format. Further note thatadditional circuitry may be used to perform serial to parallel dataconversion, parallel to serial data conversion, or the like as needed ordesired by the video processing function 68. As the data is clocked fromthe FIFO buffer 62, the video processing function 68 processes the datato provide the requested video content in a format ready for playback.The video content from the video processing function 68 is stored in theA/V playback buffer 70 for presentation to the one or more associatedviewers via the A/V interface 46.

Returning to step 404, if the playback buffer does not need more data orif the data ready signal is not active, the video buffer monitoring andtransfer control function 74 determines whether the A/V playback buffer70 is nearly full (step 410). If not, the process returns to step 402.If so, the video buffer monitoring and transfer control function 74determines whether the streaming video clock 76 is enabled (step 412).If not, the process returns to step 402. If so, the video buffermonitoring and transfer control function 74 disables the streaming videoclock 76 (step 414), and the process returns to step 402.

The RDMA enabled playback circuitry 30 provides substantial opportunityfor variation without departing from the spirit or scope of the presentinvention. For example, while the discussion above focuses primarily onvideo content, the present invention is not limited thereto. As anotherexample, while the discussion above focuses on using the RDMA enabledplayback circuitry 30 as part of a client architecture, the presentinvention is not limited thereto. More specifically, the RDMA enabledplayback circuitry 30 may alternatively be implemented in a server orheadend of a media content delivery system. In this alternativeembodiment, each of the playback buffer circuits 58-1 through 58-Y maybe allocated to a particular remote client device or a particular groupof remote client devices. The RDMA enabled FIFO buffer circuits 56-1through 56-X may be used to obtain media content for the playback buffercircuits 58-1 through 58-Y from a media content server via a LAN or WANin a manner similar to that described above. The output of the playbackbuffer circuits 58-1 through 58-Y may then be delivered to theassociated client devices via any type of delivery network such as, forexample, an Internet Protocol (IP) based delivery network. Thus, as anexample, the RDMA enabled playback circuitry 30 may be implemented aspart of the multi-client streamer of U.S. patent application Ser. No.11/760,013, entitled MULTI-CLIENT STREAMER WITH LATE BINDING OF ADCONTENT.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present invention. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

What is claimed is:
 1. A system comprising: a network interface;playback circuitry associated with the network interface comprising: afirst buffer circuit associated with the network interface andconfigured to: receive an address range of select media content defininga range of addresses in a storage unit of a media content server inwhich the select media content is stored; and perform at least onedirect memory access transfer via the network interface to transfer datastored in the address range from the storage unit of the media contentserver to the first buffer circuit; and a second buffer circuitassociated with the first buffer circuit comprising: a media contentprocessing function configured to: receive the data from the firstbuffer circuit based on a playback rate; process the data to provide theselect media content in a format ready for playback; and store theselect media content for playback.
 2. The system of claim 1 wherein thefirst buffer circuit comprises: a first buffer; and a data moverfunction configured to receive the address range of the select mediacontent and perform the at least one direct memory access transfer viathe network interface to transfer the data stored in the address rangefrom the storage unit of the media content server to the first buffer.3. The system of claim 2 wherein in order to perform the at least onedirect memory access transfer, the data mover function is furtherconfigured to: generate a first direct memory access transfer requestbased on an amount of storage available in the first buffer; issue thefirst direct memory access transfer request to the network interface,wherein data received in response to the first direct memory accesstransfer request is stored in the first buffer.
 4. The system of claim 3further comprising: a plurality of first buffer circuits comprising thefirst buffer circuit, wherein the first buffer circuit further comprisesan address compare function configured to: compare addresses of datareceived from the network interface in response to direct memory accesstransfer requests from the plurality of first buffer circuits toaddresses requested by the first direct memory access transfer requestto identify the data received in response to the first direct memoryaccess transfer request; and trigger storage of the data received inresponse to the first direct memory access transfer request in the firstbuffer.
 5. The system of claim 3 wherein in order to generate the firstdirect memory access transfer request, the data mover function isfurther configured to set a starting address of the first direct memoryaccess transfer request to a first address in the address range of theselect media content.
 6. The system of claim 5 wherein in order togenerate the first direct memory access transfer request, the data moverfunction is further configured to set an ending address of the firstdirect memory access transfer request to the starting address of thefirst direct memory access transfer request plus a value determinedbased on the amount of storage available in the first buffer.
 7. Thesystem of claim 3 wherein the first direct memory access transferrequest is for a first block of the address range determined based onthe amount of storage available in the first buffer, and in order toperform the at least one direct memory access transfer, the data moverfunction is further configured to: generate a subsequent direct memoryaccess transfer request to transfer a subsequent block of the addressrange when sufficient storage becomes available in the first buffer;issue the subsequent direct memory access transfer request to thenetwork interface, wherein data received in response to the subsequentdirect memory access transfer request is stored in the first buffer. 8.The system of claim 7 wherein in order to perform the at least onedirect memory access transfer, the data mover function is furtherconfigured to continue to generate subsequent direct memory accesstransfer requests to transfer subsequent blocks of the address rangewhen sufficient storage becomes available in the first buffer and issuethe subsequent direct memory access transfer requests to the networkinterface until transfer of the address range is complete.
 9. The systemof claim 1 further comprising: a plurality of first buffer circuitsincluding the first buffer circuit; a plurality of second buffercircuits including the second buffer circuit; and controllable switchingcircuitry configured to interconnect the plurality of first buffercircuits to the plurality of second buffer circuits in a desired manner.10. The system of claim 9 further comprising a control functionconfigured to: receive user input identifying the select media content;assign the select media content to the first buffer circuit of theplurality of first buffer circuits; identify the second buffer circuitfrom the plurality of second buffer circuits to be used for playback ofthe select media content; and control the controllable switchingcircuitry to interconnect the first buffer circuit to the second buffercircuit.
 11. The system of claim 1 wherein the second buffer circuitfurther comprises a clock generation function configured to provide aplayback clock.
 12. The system of claim 11 wherein the clock generationfunction is controlled based on user input controlling playback of theselect media content.
 13. The system of claim 1, wherein the networkinterface and the playback circuitry are in a set top box.
 14. Thesystem of claim 1, wherein the network interface and the playbackcircuitry are in a server.
 15. The system of claim 1, wherein thenetwork interface and the playback circuitry are in a head end of amedia content delivery system.
 16. A method comprising: performing atleast one direct memory access transfer via a network interface totransfer data stored in an address range for select media content from astorage unit of a media content server to a first buffer circuit; andtransferring the data from the first buffer circuit to a second buffercircuit based on a playback rate; processing the data to provide theselect media content in a format ready for playback; and storing thedata to enable playback of the select media content.
 17. The method ofclaim 16 wherein performing the at least one direct memory accesstransfer comprises: generating a first direct memory access transferrequest based on an amount of storage available in a first buffer of thefirst buffer circuit; issuing the first direct memory access transferrequest via the network interface; receiving data in response to thefirst direct memory access transfer request; and storing the datareceived in response to the first direct memory access transfer requestin the first buffer of the first buffer circuit.
 18. The method of claim17 wherein receiving the data in response to the first direct memoryaccess transfer request comprises: receiving data in response to aplurality of direct memory access transfer requests comprising the firstdirect memory access transfer request issued by a plurality of firstbuffer circuits comprising the first buffer circuit; comparing addressesof the data received in response to the plurality of direct memoryaccess transfer requests to addresses of the first direct memory accesstransfer request to identify the data received in response to the firstdirect memory access transfer request; and triggering storage of thedata received in response to the first direct memory access transferrequest in the first buffer of the first buffer circuit.
 19. The methodof claim 17 wherein generating the first direct memory access transferrequest comprises setting a starting address of the first direct memoryaccess transfer request to a first address in the address range of theselect media content.
 20. The method of claim 17 wherein the firstdirect memory access transfer request is for a first block of theaddress range determined based on the amount of storage available in thefirst buffer of the first buffer circuit, and performing the at leastone direct memory access transfer further comprises: generating asubsequent direct memory access transfer request to transfer asubsequent block of the address range when sufficient storage becomesavailable in the first buffer of the first buffer circuit; issuing thesubsequent direct memory access transfer request via the networkinterface; receiving the data in response to the subsequent directmemory access transfer request; and storing the data received inresponse to the subsequent direct memory access transfer request in thefirst buffer of the first buffer circuit.
 21. The method of claim 20wherein performing the at least one direct memory access transferfurther comprises continuing to generate subsequent direct memory accesstransfer requests to transfer subsequent blocks of the address rangewhen sufficient storage becomes available in the first buffer of thefirst buffer circuit and to issue the subsequent direct memory accesstransfer requests to the network interface until transfer of the addressrange is complete.
 22. The method of claim 16 wherein the first buffercircuit is one of a plurality of first buffer circuits and the secondbuffer circuit is one of a plurality of second buffer circuits, and themethod further comprises interconnecting the first buffer circuit to thesecond buffer circuit via switching circuitry.
 23. A computer programproduct stored on a non-transitory computer-readable storage medium andincluding instructions configured to cause a processor to carry out thesteps of: performing at least one direct memory access transfer via anetwork interface to transfer data stored in an address range for selectmedia content from a storage unit of a media content server to a firstbuffer circuit; transferring the data from the first buffer circuit to asecond buffer circuit based on a playback rate; processing the data toprovide the select media content in a format ready for playback; andstoring the data to enable playback of the select media content.
 24. Asystem comprising: a media content server; a network interface; playbackcircuitry associated with the network interface comprising: a firstbuffer circuit associated with the network interface and configured to:receive an address range of select media content defining a range ofaddresses in a storage unit of the media content server in which theselect media content is stored; and perform at least one direct memoryaccess transfer via the network interface to transfer data stored in theaddress range from the storage unit of the media content server to thefirst buffer circuit; and a second buffer circuit associated with thefirst buffer circuit comprising: a media content processing functionconfigured to: receive the data from the first buffer circuit based on aplayback rate; process the data to provide the select media content in aformat ready for playback; and store the select media content forplayback.
 25. The system of claim 24, wherein the network interface andthe playback circuitry are in a set top box.
 26. The system of claim 24,wherein the network interface and the playback circuitry are in aserver.
 27. The system of claim 24, wherein the network interface andthe playback circuitry are in a head end of a media content deliverysystem.
 28. The system of claim 24, wherein the media content server islocated in a head end of a media content delivery system.